In known III-Nitride HEMT devices used in power applications, there exists a design trade-off between the on-state resistance and breakdown voltage (BV). Known high voltage GaN HEMT devices use a technology and process flow based on a lateral device structure where a large drift region supports the off-state voltage that extends laterally, and where a high mobility 2DEG sheet is oriented horizontally.
FIG. 1A illustrates a cross-section of a portion of a prior art high voltage HEMT 10 comprising a narrow-bandgap channel layer 12, or carrier carrying layer, for example of undoped GaAs or GaN, formed on top of a buffer structure 13 itself formed on top of a substrate 14 such as a Si substrate. A wide-bandgap carrier supplying layer 15, or barrier layer, for example a highly-doped n-type AlGaAs or AlGaN layer, is formed on top of channel layer 12. HEMT 10 comprises a channel region 16 formed in channel layer 12 between a conductive source region 17 and a conductive drain region 18 both formed through the carrier supplying layer 15 into channel layer 12. A passivation layer 19 covers carrier supplying layer 15 above the channel region 16. A gate region 20, insulated by an insulator layer 21, traverses the passivation layer 19 into the carrier supplying layer 15. Alternatively, gate region 20 insulated by insulator layer 21 can traverse the passivation layer 19 to come in contact with the surface of carrier supplying layer 15. In addition, HEMT 10 comprises field plates 22, 23 attached respectively to gate region 20 and source region 17.
In HEMT 10, the drift region which extends from the edge of gate region 20 to the drain region 18 is oriented horizontally with the function of supporting high drain to source and high drain to gate voltage during the off-state operation. A second important feature of HEMT 10 is a two dimensional electron gas layer 24 which forms in the carrier carrying layer 12 right below the interface between the carrier supplying layer 15 (AlGaN) and the carrier carrying layer 12 (GaN layer). 2DEG layer 24 has a high carrier mobility that can for example reach 2100 cm2/V·sec. If the AlGaN layer thickness is increased beyond a certain value, a 2DEG will form under the interface with the density of 2DEG increasing with both the thickness of the AlGaN layer and the Al mole fraction.
A horizontal 2DEG HV GaN based HEMT such as lateral HEMT 10 is considered, at the present time, to be a preferred candidate to lead the power electronics roadmap due to its superior material properties such as high critical electric field, wide band-gap and high saturation velocity as well as the ability to utilize a high density of sheet charge that can move in the 2DEG layer with high mobility. However, for higher voltage devices with ratings for example above 600V, the horizontal drift region becomes relatively large which in turn results in a larger cell pitch and higher product of on-state resistance and chip area Ron.A, where A is the area of the device chip.
The product Ron.A is an important figure of merit in power devices as it directly impacts the cost of the die. A further impact on die cost comes from a lower yield associated with larger die area which is particularly significant for lateral GaN.
While still more favorable than their Silicon counterparts, High Voltage GaN based lateral HEMTs become less attractive than vertical GaN based devices as the blocking voltage increases due to the requirement for longer drift region to support the off-state drain voltage.
FIG. 1B illustrates a cross-section of a portion of a prior art high voltage super junction MOSFET 25 as disclosed for example in US2015/0021686 to Shea. Super junction MOSFET 25 is formed from a P-doped base substrate material 26, and includes P-channel area 27, P+ source contact region 28, N+ source contact region 29, and N+ drain contact region 30. A gate dielectric 31 is formed over base substrate material 26, and polysilicon (poly) gate 32 is formed over the gate dielectric. A super junction structure comprising N-doped stripes 33 and P-doped stripes 34 runs from an area under poly gate 32 to N+ drain contact region 30. N-doped stripes 33 include a width Wn. P-doped stripes 34 include a width Wp. Stripes 33 and 34 include a junction depth into base substrate material 12, Xj, which is the same for each stripe. Stripes 33 and 34 are doped as heavily as possible while still fully depleting prior to the breakdown of MOSFET cell 30. The super junction is used to provide as much heavily doped area between N+ drain contact region 30 and poly gate 32 as possible.
The super junction removes the relationship between BVdss and doping concentration, as is the case with a conventional MOSFET cell that would use an LDD, or drift, region between N+ drain contact region 30 and poly gate 32. A higher doping concentration is used in the super junction as compared to a LDD region, resulting in lower RDSON. MOSFET 25 improves the RDSON of the MOSFET without a significant increase in Qg, resulting in a net reduction of total power loss.
The super junction in MOSFET 25 maintains a high BVdss despite a high doping concentration by replacing the depletion region between a known LDD region and the base substrate material with a plurality of depletion regions between each adjacent N-doped stripe 33 and P-doped stripe 34. Stripes 33 and 34 deplete each other instead of base substrate material 26, therefore the electric field of the super junction is oriented laterally.
FIG. 1C illustrates the electric field of the super junction in the off-state of MOSFET 25C. In the off-state of MOSFET 25, charge carriers in the stripes 33 and 34 deplete by drifting under the electric field towards their respective contacts, leaving behind bound ion charges which are negative acceptor atoms in the p-stripes and positive donor ions in the n-stripes. If the opposite bound ion charges are equal in magnitude and closely spaced, the net effective charge will sum to a net zero value. The consequence of this net zero value of charge, according to the Poisson's equation, is a flat electric field distribution as illustrated in FIG. 1C. The advantages of the Super Junction does not come without constrains which is mainly set by the requirement for tight fabrication control to ensure charge balance between the n and p pillars, in addition to the need for multiple fabrication steps.
The doping concentrations of stripes 33 and 34 are calibrated such that the stripes fully deplete prior to breakdown of MOSFET cell 25. After stripes 33 and 34 are fully depleted, the voltage at drain contact region 30 is supported by the length, Lsj, of the super junction. When the super junction is fully depleted, the electric field from applied voltage at N+ drain contact 30 to poly gate 32 is oriented lengthwise through the super junction. Making stripes 33 and 34 longer increases BVdss by stretching the electric fields over a longer distance, reducing the magnitude of the electric fields. However, despite improved properties, super junction MOSFET 25 still introduces a significant cell pitch.
In a vertical configuration (vertical power device) the cell pitch is reduced significantly because the drift region extends vertically. The lateral dimension in such structure is limited only by process constraints and punch-through breakdown considerations. This implies that the Ron.A product will be much lower for the vertical device as compared to lateral devices and this is especially true for higher voltage ratings.
FIG. 2 illustrates a cross-section of a portion of a known vertical GaN FET 40 comprising a substrate 42, for example made of N+GaN, on top of which is arranged a drift layer 44 for example made of low doped N− GaN. The FET 40 comprises no 2DEG and no super junction. A channel layer 46, for example of undoped GaN, is arranged on top of drift layer 44 and is covered by a source contact region 48. Source contact region 48 and channel region 46 are traversed by a gate trench 50 that extends into drift region 44. A gate insulator layer 52 lines the gate trench 50 and a gate contact region 54 fills up the space left in the gate trench by the gate insulator layer 52. A drain electrode 56 is arranged on the bottom surface of substrate 42; source and gate electrodes contact the source and gate contact regions, on the top surface of FET 40. FET 40 comprises a drift region 58 that extends vertically in the drift layer 44, whereby current conduction in FET 40 is vertical and the voltage across the device in the off-state is supported across the vertically-oriented drift region.
The vertical configuration of FET 40 translates into a significant reduction of the cell pitch for a transistor having a high voltage rating. The cell pitch for a vertical device such as FET 40 is mainly determined by photolithography, process constrains to implement the vertical structure and punch through considerations. For a given technology maturity level of a vertical power device such as GaN FET 40 and lateral power device such as Gan HEMT 10, a breakeven point of the voltage rating in terms of value proposition is set. Below the breakeven point, the lateral configuration makes more business sense and above it the vertical configuration is more favorable. The breakeven point can be determined by the drift region length (which is design related), cell pitch, cost of starting material in addition to process complexity and mask count of each of the two configurations.
Known vertical GaN-based devices rely on bulk GaN drift region in which the high electron density and high mobility layers are absent. Bulk GaN devices rely on bulk mobility, which is considerably lower than the 2DEG mobility. The inventors have noted that for high voltage devices with voltage ratings larger than 600V, vertical GaN HEMTs would often be preferable compared to lateral GaN HEMT.
Furukawa U.S. Pat. No. 7,038,253 B2 issued on May 2, 2006 discloses a GaN-based field effect transistor of a normally-off type, which has an extremely small ON resistance during operation and is capable of a large-current operation, which comprises source and drain electrodes; a channel portion made of a first GaN-based semiconducting material that is an i-GaN-based semiconducting material or a p-GaN-based semiconducting material. The channel portion is so formed as to be electrically connected to the source and drain electrodes. First and second electron supply portions made of a second GaN-based semiconducting material have greater bandgap energy than the first GaN-based semiconducting material, the first and second electron supply portions being joined to the channel portion and located separately from each other. An insulating layer, formed on the surface of the channel portion, spreads between the first and second electron supply portions; and a gate electrode is disposed on the insulating layer.
Rohm Co. U.S. Patent Application Publication US 2009/0057684 to Hirotaka entitled “Nitride Semiconductor Device and Method for Producing Nitride Semiconductor Device” discloses a Nitride semiconductor device that includes: a semiconductor base layer made of a conductive group III-Nitride semiconductor having a principal plane defined by a nonpolar plane or a semipolar plane; an insulating layer formed on the principal plane of the semiconductor base layer with an aperture partially exposing the principal plane; a Nitride semiconductor multilayer structure portion, formed on a region extending onto the insulating layer from the aperture, having a parallel surface parallel to the principal plane of the semiconductor base layer as well as a +c-axis side first inclined surface and a −c-axis side second inclined surface inclined with respect to the principal plane of the semiconductor base layer and including two types of group III Nitride semiconductor layers at least having different lattice constants; a gate electrode formed to be opposed to the second inclined surface; a source electrode arranged to be electrically connected with the group III Nitride semiconductor layers; and a drain electrode formed on a back surface of the semiconductor base layer opposite to the principal plane.
U.S. Pat. No. 7,098,093 to Clarke discloses a HEMT type device which has pillars with vertical walls perpendicular to a substrate. The pillars are of an insulating semiconductor material such as GaN. Disposed on the side surfaces of the pillars is a barrier layer of a semiconductor material such as AlGaN having a bandgap greater than that of the insulating material of the pillars. Electron flow is confined to a narrow channel at the interface of the two materials. Suitable source, drain and gate contacts are included for HEMT operation.
U.S. patent application Ser. No. 14/329,745 discloses a vertical HEMT wherein at least a portion of the drift region between the gate and the drain relies on 2DEG mobility. The HEMT device comprises a III-Nitride material substrate, the surface of which follows a plane that is not parallel to the C-plane of the III-Nitride material; an epitaxial layer of III-Nitride material grown on said substrate; a recess etched in said epitaxial layer, having at least one plane wall parallel to a polar plane of the III-Nitride material; a carrier supply layer formed on a portion of the plane wall of the recess, such that a 2DEG region is formed along the portion of the plane wall of the recess; a doped source region formed at the surface of said epitaxial layer such that the doped source region is separated from said 2DEG region by a channel region of the epitaxial layer; a gate insulating layer formed on the channel region of the epitaxial layer; and a gate contact layer formed on the gate insulating layer.
U.S. Philips Corp. U.S. Pat. No. 4,754,310, issued, June 1988, discloses a Silicon based device structure applicable to FETs, bipolar, diodes etc., and uses an alternatively doped structures to support high reverse bias voltage during the blocking mode of operation.
University of Toronto, U.S. Patent application No US2003/0190789, issued October 2003, is a lateral Super Junction power MOSFET implemented on Si-On-Insulator substrates to eliminate substrate-assisted-depletion inherent in the lateral Super Junction structure.
Unpublished U.S. patent application Ser. No. 14/471,980 to Rongming Chu discloses a vertical trench MOSFET using a III-N material.